1. Field of the Invention
This invention relates to high density integrated circuit (IC) structures, and more particularly to a multi-layer assembly employing discrete IC chips.
2. Description of the Related Art
There is a continuing need for microelectronic systems employing high density circuits with many data lines. Such systems are conventionally constructed with prefabricated IC circuits sealed in packages, mounted on printed circuit boards and provided with interconnections between the circuit packages by means of connectors, backplanes and wiring harnesses. To reduce the size, weight and power consumption of such systems, multiple chips can be sealed inside a single package.
A much higher level of integration at the lowest packaging level has been achieved with a new 3-D microelectronics technology which reorganizes the physical structure and approach to parallel computing and memory. In one application, a 3-D computer employs a large number of parallel processors, typically 10.sup.4 -10.sup.6, in a cellular array configuration. A wide variety of computationally intensive applications can be performed with substantial system level advantages. To handle the very large number of data lines (typically 10.sup.4 -10.sup.6), a stacked wafer approach is taken, with electrical signals passing through each wafer by means of specially processed feedthroughs. The wafers are interconnected by means of microbridge spring contacts.
The 3-D computer is described in U.S. Pat. Nos. 4,507,726 to Grinberg et al. and 4,707,859 to Nudd et al., both assigned to Hughes Aircraft Company, the assignee of the present invention. A plurality of elemental array processors are formed from a vertical stack of modules, with the modules arranged as functional planes; modules of a similar functional type are located on each plane. The various planes are implemented as separate wafers, each wafer having a unitary IC distributed over its upper surface with monolithically integrated interconnections between circuit elements. Interconnections between adjacent wafers in the stack are formed by electrically conductive feedthroughs which extend through the wafers from the IC on the upper surface to the lower surface, and a collection of microbridge spring contacts on both the upper and lower sides of the wafers. The spring contacts on the upper sides of the wafers make electrical contact with selected locations on the IC, while the spring contacts on the bottom electrically connect to selected feedthroughs. The spring contacts are positioned so that the ones on top of the wafer bear against and electrically connect to corresponding spring contacts on the bottom of the next wafer above. The feedthroughs can be formed by a thermal migration of aluminum, while the spring contacts are implemented as microbridges. Both techniques are described in U.S. Pat. Nos. 4,239,312 and 4,275,410, assigned to Hughes Aircraft Company.
While the processor described above provides a very high density of circuitry, it is limited in the sense that a custom designed IC is fabricated on each wafer, and that wafer can serve no other purpose. Furthermore, each wafer is generally limited to a single class of circuitry (CMOS bipolar, I.sup.2 L, etc.). A different approach to high density circuit packaging which provides a greater degree of freedom in the flexibility of circuit design involves the use of discrete chips mounted to a substrate and interconnected by means of wire bonding to a metallized interconnection network on the substrate surface. With wire bonding, all of the input/output ports for each chip are located around the periphery of the chip. Because of the area required to route signals to and from the periphery of the chip, typically only about 40% of the chip and substrate surface area is available for the actual circuitry, with about 60% dedicated to the input/output connections. In addition to a relatively inefficient use of chip and substrate surface area, the greater overall chip area required for a given amount of circuitry increases the rate of defects and reduces the manufacturing yield. Furthermore, the wire bond connections can reduce the circuit's speed of operation, and makes it difficult to use bulk attachment techniques in the manufacturing process. Similar problems apply to conventional "TAB" (tape automated bonding) connections.
A more recently developed approach to the placement of discrete IC chips on a substrate is the "flip chip" method. Rather than positioning the chip with the circuitry facing up and TAB or wire bonding from the substrate to the top of the chip, with the flip chip technique the chip is turned upside down, with connections made to the substrate metallization network by solder "bump" bonding. A subsequent wire bonding step after the chips have been mounted is thus eliminated. The flip chip technique is discussed, for example, in Pfeiffer et al., "Self-Aligned Controlled Collapse Chip Connect (SAC4)", Journal of the Electro-Chemical Society: Solid-State Science and Technology, Nov. 1987, pages 2940-2941, and T. Kawanobe, "Interconnection of Semiconductor Elements to Ceramic Substrates", Ceramics Japan, Mar. 1986 pages 201-206.
While eliminating some of the problems associated with TAB and wire bonding, the flip chip approach has its own limitations. First, there are problems in properly aligning the chip with the interconnect routing on the substrate. Since the process of cutting out the chip from its original wafer is not completely coordinated with the positioning of the input-output pads, the positions of the pads cannot be precisely predicted based upon the shape of the chip after it has been flipped over. Accordingly, complex and expensive attachment techniques are required to accurately attach the chips to the substrate. Also, for large chips having many closely spaced input/output pads around the edge, it is difficult to solder the pads to the substrate routing without the solder squeezing out to adjacent pads. Furthermore, the fact that the chips are mounted upside down precludes visual inspection after the assembly has been completed, and thus rules out the flip chip method for certain applications in which visual inspection is part of mandatory quality control procedures. It also precludes the use of "universal designs", i.e., the use of wire bonds or solder bumps.